At present, the vast majority of microprocessors and computer systems are synchronous systems that incorporate system clocks and “globally” synchronous buses. In particular, synchronous buses are presently, and most likely will be for some time, the buses of choice and several “standard” buses are known, and designed to, within the electronics industry. In the prior art, the speed at which data could be transmitted on a synchronous bus was limited by the inherent maximum latency between a source and a target within the system. In other words, the minimum time between transfers of data on a synchronous bus had to be greater than the maximum time it took to transmit a signal from a source to a target within the system to avoid significant skew between the clock and the data.
At relatively slow bus speeds, such as those below 100 MHZ, the fact that the maximum speed of the synchronous bus was limited by the maximum latency was not particularly problematic and could be dealt with using prior art methods. However, higher bus speeds, such as 200 MHZ, are rapidly becoming the norm and even greater bus speeds are being sought and developed for future systems. Unfortunately, these higher bus speeds mean that even small amounts of skew between the clock and the data can very problematic and can result in an asynchronous data flow. If not corrected, this situation results in increased system errors or system failure.
In some prior art systems, and particularly in SDRAM systems, single level First-In/First-Out (FIFO) circuits were employed. However, the use of single level FIFOs was only marginally successful because these systems were skew intolerant, generally inflexible and, when error was introduced, there was no recourse or correction mechanism. One prior art “fix” to the skew problem was to include a feedback clock and a single register to correct/control skew between data and the system clock. However, this “fix” proved of limited value because it was still based on a single level/single register solution and therefore lacked sufficient skew tolerance and flexibility.
Since limiting bus speeds to 100 MHZ or less is simply not an acceptable solution, designers have been forced to turn to complicated and expensive solutions such as new or highly modified, i.e., non-standard, buses, very deep and non-traditional FIFOs and complicated systems and solutions typically associated with experimental asynchronous systems. This has resulted in increased system complexity, non-standardization of systems and increased cost. To make matters worse, even these expensive and complicated solutions have met with very limited success and have therefore not been widely implemented.
What is needed is a method and apparatus to improve the performance of a standard synchronous bus such that the synchronous bus can transmit data at a rate faster than the traditional limit imposed by the maximum latency between a source and a target within the system, while, at the same time, providing system flexibility, adding minimum complexity and introducing minimum added logic latency.